codasip disaznirao 3 RISC-V Linux ready jezgraCitat:
The A70XP adds a SIMD (single instruction, multiple data) unit that executes RISC-V P extension instructions with single-cycle latency. Multi-cycle instructions are pipelined to allow one to be executed every clock cycle. The extensions are said to enable audio encoding/decoding, sensor fusion, computer vision, and edge AI/ML applications.
Andes Technology offers P extension support on its 45-series cores including the recent AndesCore A45MP and AX45MP via an optional DSP. The similar naming scheme between the Codasip and Andes cores are confusing, but logical: In both cases, the A stands for application processor and the MP stands for multiprocessor (multi-core) support.
Codasip does not explain the difference between the new, multi-core ready A70X-MP and A70XP-MP, but judging from the naming scheme, the A70X-MP is a multi-core ready version of the A70X and the A70XP-MP is the multi-core version of the new P-extension enabled A70XP. Both MP processors support clusters of up to four cores in an SMP (symmetric multi-processor) configuration. They also offer configurable L1 and L2 caches with a scalable microarchitecture.
